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JET60200's avatar
JET60200
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5 years ago

Error (17045): Input port I of I/O input buffer primitive |emif_0| .. |gen_mem_alert_n.inst[0].b|no_oct.ibuf is not connected

I'm writing an project to access system ddr4 (read & write). In Quartus Pro 19.2 Platform designer, I added "EMIF IP" inside, and add a top.v as well. ​ But when trying to compile, it reports so...
JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago

continue ..

​

in << External Memory Interface Handbook Volume 2: DesignGuidelines。pdf >>

  • 7.4.3.2. Arria 10 EMIF IP DDR4 Parameters: Memory

​

there mentions as below: " Enable ALERT#/PAR pins - MEM_DDR4_ALERT_PAR_EN " which describes as following- " .. Allows address/command calibration, which may provide better margins on the address/command bus. .

The parity pin is a dedicated pin in the address/command bank, but the alert_n pin can be placed in any bank that spans the memory interface. You should explicitly choose the location of the alert_n pin and place it in the address/command bank.

"

​

Could I disable this " Enable ALERT#/PAR pins " in Arria 10 SOC ? If it's mandatory pin, how should I assign pin for it (alert_n) ? Thanks great for any help.

​

/jet ​

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

By right you will see a RZQ pin in the IP top level file. You need to export this pon to top level and assign with an input pin.