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jerry_anto's avatar
jerry_anto
Icon for New Contributor rankNew Contributor
3 years ago

Error (14996): The Fitter failed to find a legal placement for all periphery components

I'm using Cyclone V GX board and in that lvds_rx and mipi ports are on bank 4a, so we need at least 2 pll ( one for lvds and one for mipi signals) The compiler is trying to place both in the sam...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Please refer to the Cyclone V Handbook and the pinout file for the device. As per the pinout file there are 2 clock pins i.e. CLK2p/n and CLK3p/n in Bank 4A. Handbook shows the accessibility of the pins to the PLLs. As you can see below there are 2 PLLs which are available. As per your pin assignments, the two pins CLOCK_80M and SWIR_CL_SCLK already occupy these two PLLs. There is no way that any other clock pin can access these PLLs now. So, you will have to relocate the pins as per PLL availability of the bank pins.

Hope this info helps identify the issue.

Regards