Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi All
I'm having a very similar problem, and maybe for you could be easier to help me to solve: I can't perform a right association between LCD and NIOS into vhdl code main project that create the connection between entities. In particular I can't exactly understand why SOPC builder create the following interface for LCD: component lcd_0 is port ( -- inputs: address : IN STD_LOGIC_VECTOR (1 DOWNTO 0); begintransfer : IN STD_LOGIC; clk : IN STD_LOGIC; read : IN STD_LOGIC; reset_n : IN STD_LOGIC; write : IN STD_LOGIC; writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- outputs: LCD_E : OUT STD_LOGIC; LCD_RS : OUT STD_LOGIC; LCD_RW : OUT STD_LOGIC; LCD_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); end component lcd_0; How can I connect all these "signals" with processor? Could anyone help me? Thanks