Enabling Intel® Stratix® 10 H-Tile and L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express* on S10-DX kit

I am able to follow the guide, able to generate example design and generate SOF file.

next task - I want to extended the config address space mapping for PCIe IP above 0xFFh (to use and define PCIe DVSEC capability registers), and assign some predefined values to certain addresses in “Read Only” mode.

While generating PCIe IP through IP catalog , there was no option to define extended config space or DVSEC registers. so in order to do what i want, I started reviewing RTL files; generated by PCIe IP compilation in Quartus. Many of the files appears to be encrypted (see the screenshot); and I can not read the RTL code associated with these modules. Do you know how to decrypt these RTL files? So I can read them and identify lines of code, which needs to be modified.