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Altera_Forum's avatar
Altera_Forum
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17 years ago

DSP Development Kit, Stratix II Ed

Normally, design file download is well working.. but, sometimes the development kit initialized after downloading.... I think it is totally doesn’t make sense...what is probably cause this
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

ok tempeku i have solved my issue, hopefully this will solve yours too.

in Quartus goto Assignments -> Settings -> Device

click Device and Pin Options

click the Unused Pins tab

change the reserve all unused pins field to "As input tri-stated with weak pull-up resistor"

my unused pins were set to drive ground by default which caused the fpga to read the configuation prom about half the time. now it reads my sof 100% of the time.