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Occasional Contributor

3 years ago

Downtrain to PCIe Gen3x8 when generating Quartus design with Avalon-MM+ IP for S10 GX dev kit

Avalon® memory mapped Intel® Stratix® 10 Hard IP+ for PCI Express* Solutions User Guide shows that Avalon-MM+ IP can support Gen8 x 16 for PCIe. When I genetate a design with the IP, I find ...

skbeh

Contributor

3 years ago

Hi sir

1) Please check to ensure your rootport CPU is also capable support up to gen3x16.

2) Instead of using the IP tab generated example design, please try use this Example Design from AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with DDR4 SDRAM and HBM2 Memories Reference Design

Below is the document and design link:

https://www.intel.com/content/www/us/en/docs/programmable/683291/current/introduction.html

He4Forum

Occasional Contributor

3 years ago

Hi skbeh,

I notice that the design you shared to me is for Intel® Stratix® 10 MX FPGA Development Kit, while I am using Intel® Stratix® 10 GX FPGA Development Kit. So will this cause any issue?

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Downtrain to PCIe Gen3x8 when generating Quartus design with Avalon-MM+ IP for S10 GX dev kit

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