Forum Discussion
BoonT_Intel
Frequent Contributor
6 years agoYes, Figure 25 better illustrate the setup and hold requirement for the data latching.
Lambert
Occasional Contributor
6 years agoHi BCT_Intel
I am leaning the source synchronization constrains, but I am confused about centric-FPGA method just because that there is no complete diagram to illustrate the relationship about vritual clk, input/output clk and data input/output liking internal reg-to-reg. And I don't know how the quartus II to complete route based on the information. Can you provide me some help about this? I have watch the training class, I can't complete understand this method.
Best regards,
Lambert