Forum Discussion

msc's avatar
msc
Icon for New Member rankNew Member
5 hours ago

Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit

We will use the SOM Module of the Agilex 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1) for a new project with our own designed carrier board.

For this design we need multiple differential transmit and receive signals from I/O Bank 2A_B and 2A_T (→ 1.2V bank supply).

We started with a basic design to evaluate usable I/O Standards.

We have seen that we can use differential receiver with the 1.2V bank supply but it is not possible to use "True Differential Signaling" on transmit pins with 1.2V bank supply.

 

For our purpose it is necessary to generate differential transmit signals correctly working with LVDS inputs on the receiver site.

 

Is there an alternative differential signal output generating a correct LVDS signal for a LVDS receiver working with the 1.2V bank supply (e.g. POD12 with special termination)?

What happens when setting differential transmit and receive pins to "1.3V True Differential Signaling" to get Quartus running without an error but physically using only 1.2V bank supply?

Will this only decrease signal swing on transmit pins or is this not working?

Or could this damage the FPGA transmit and receive pins of the FPGA?

The SOM schematic does not show any possibility to disconnect the I/O Banks 2A_B and 2A_T from onboard 1.2V supply to use an alternative external 1.3V supply.

Is there the a possibility to supply these banks externally by 1.3V?

Which other alternatives do we have to get differential signaling output working?

1 Reply

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor

    Hi,
    Agilex 5 065B SoM has fixed 1.2 V supplied to Bank 2A. The same power supply rail is also supplying other 1.2 V loads and can't be changed on the module.

    Original LVDS spec (TIA 644, IEEE Std 1596.3) have rather tight Vocm spec of 1.25 V +/- 10% (1.125 to 1.375 V). It's not achieved by TDS 1.3V IO-standard with Vocm range of 0.9 to 1.1 V. To meet LVDS Vocm spec strictly in a 1.2 V supplied bank, you'd need a resistor network with external voltage offset. 

    Most LVDS receivers have however much wider Vicm range than required by the standard, respectively they can tolerate deviating driver Vocm. Possible range also depends on data rates, see as an example Cyclone 10 GX LVDS receiver spec.

    I'm quite sure that TDS 1.3 V IO-standard won't fail if the bank is actually supplied, Vocm will be respectively lower but still accepted by most LVDS receivers.

    If it's an acceptable solution for your project depends on many prerequisites that we don't know.

    Regards
    Frank