Diff Clk pins used as I/O on a Cyclone 10 LP

Hi, previous post dosn't seem to answer your specific question.

I unerstand that you want to use CLK pins with single ended clock signal. In this case, p and n pin of a pin pair are independent. You can e.g. use CLK0 (DIFFCLK_0p) as clock input and CLK1 (DIFFCLK_0n) as user input signal.

Generally, refer to current pin connection guideline https://www.intel.com/content/www/us/en/docs/programmable/683137/current.html

and test the chosen pin configuration in Quartus.