Mahdi
Occasional Contributor
Occasional ContributorDesign Partition help
Hello all,
I have several questions regarding design partitioning in Quartus. What I am doing right now is to connect a custom IP core (let's call X) to a NIOS II and on-chip memory in my system. A...
1) Yes.
2) That depends. It might be because the Logic Lock region is limiting the placement and routing options for the partition, so the performance is not as good as without the LL region. If you don't need an LL region, don't enable it to give the Fitter more freedom. However, with the design reuse flow that it sounds like you want to do, you would need an LL region to reserve a location for a design partition in another design.
3) Yes. This is the design reuse flow.
See the block-based design user guide and associated training for details:
