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I couldn't able to find any timing constrains are given for SSRAM interface.
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That is unfortunate. Poor examples teach bad habits. No example design should be provided without good timing constraints.
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Let me try to use PLL clk for SSRAM module and given some constrains for the interface. I will update you my results asap.
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That should be sufficient to get things working.
If you need an example of an .SDC file, I created one for the Altera SDRAM controller in this DE0-nano example ...
http://www.alteraforum.com/forum/showthread.php?t=45927 Cheers,
Dave
Honored Contributor
