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Altera_Forum
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17 years ago

DE2 SRAM Flash & Tristate Bridges

Hi, in the example DE2 designs for NIOSII SOPC systems, the SRAM is connected directly to the Avalon Bus while the Flash is connected via a tristate bridge. What is the reason for that? In th...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

SRAM and Flash are connected by separate individual address and data busses to the FPGA. Both data busses are bidirectional, SRAM is 16 bit and Flash is 8 bit.