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Altera_Forum
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17 years ago

DE2 SRAM Flash & Tristate Bridges

Hi, in the example DE2 designs for NIOSII SOPC systems, the SRAM is connected directly to the Avalon Bus while the Flash is connected via a tristate bridge. What is the reason for that? In th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

what do you mean address/data bus sharing? not clear.

My understanding is that if avalon IF data(as opposed to fpga pins) is bidirectional then you need tristate bridge.

I don't know about DE2 but I will assume avalon data is bidirectional for flash but separate input/output for sram(then bidirectional at fpga pins through your tristate bridge).