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Honored ContributorDE2 Sdram
Hi all !!, my name is Alberto. I'm a very begginer in FPGA's. Most experience in microcontrollers. I'm trying to learn some about this, with the Altera DE2 board. I'm trying to test SDRAM cod...
Altera_ForumHonored Contributor
Honored ContributorHello Alberto,
yes, the VHDL code is the Altera reference design I used in my applications. I found some indications, that it may have been ported from Verilog, e. g. there is a comment about an always block. The VHDL design could be implemented rather easily as far as I remember, the only change I applied was to assign a fast output enable register to the datapath OE signal, that would be a bit late otherwise. Good luck, Frank
