Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi
Again please lets take an example. in DE2.VHD top, I just need to connect all port. e.g. I have: port ( -- Input clocks clk_50MHz : in std_logic; clk_27MHz : in std_logic; clk_sma : in std_logic; -- SDRAM sdram_clk : out std_logic; sdram_cke : out std_logic; sdram_csN : out std_logic; sdram_rasN : out std_logic; sdram_casN : out std_logic; sdram_weN : out std_logic; sdram_ba : out std_logic_vector( 1 downto 0); sdram_addr : out std_logic_vector(11 downto 0); sdram_dqm : out std_logic_vector( 1 downto 0); sdram_dq : inout std_logic_vector(15 downto 0); etc. So I need to see that in my constrains file I have same names. And if not -> should fix it in DE2.VHD file lets take from DE2.VHD more example, I have in file port: -- LCD lcd_on : out std_logic; now in constrains.tcl I have line with: set_location_assignment PIN_L5 -to LCD_ON ;# LCD Back Light ON/OFF (not working) so since they both LCD_ON (except capital letters, does it matter?) => so this is all good, and this port doesn't need any change at all. Right? Thanks, Roee