--- Quote Start ---
The TOP LEVEL is DE2.VHD (vhdl file) and not HDL? - is this correct (I don't see any HDL file in project directory)
--- Quote End ---
HDL just means hardware description language. In my design I used de2.vhd as the top-level HDL file. You could just as easily use a .BDF file.
--- Quote Start ---
When I changed the "constrains.tcl" pin assignment -> I already declared the DE2-115 pin out
--- Quote End ---
Editing the file is not enough. You have to 'source' the file via the Tcl console to change your project settings.
--- Quote Start ---
So what file hold the connection between the Altera chip and TOP level?
--- Quote End ---
You tell Quartus what your top-level design file is. The pin names on the top-level, along with the matching pin assignments defines the top-level pins at the FPGA level.
--- Quote Start ---
The .PIN file is same like going in menu to Assigments -> pins correct?
--- Quote End ---
No. The .pin file is generated during synthesis. Look at the report files.
Cheers,
Dave
Honored Contributor
