Hi,
when you say
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You have to have matching pin assignment constraints and top-level HDL pin names. Review the .pin file generated by Quartus until things match.
You're on the right track. Now you have to make sure your top-level HDL names match and check the .pin file.
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Just to clarify that I have understood:
When I changed the "constrains.tcl" pin assignment -> I already declared the DE2-115 pin out, so now I have to use these names in project TOP LEVEL.
The TOP LEVEL is DE2.VHD (vhdl file) and not HDL? - is this correct (I don't see any HDL file in project directory)
So what file hold the connection between the Altera chip and TOP level?
The .PIN file is same like going in menu to Assigments -> pins correct?
Thanks,
Roee
Honored Contributor
