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Altera_Forum
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13 years ago

DE2-115 : position of data pin of FLASH and SDRAM

Hi, I have a DE2-115 and I try to understand how memories are interfaced. In the "External Memory Interface in Cyclone IV Devices" book I read : Cyclone IV devices use data (DQ), data strob...
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Altera_Forum
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13 years ago

DQS is a double-data-rate DDR SDRAM signal. The DE2-115 contains single-data-rate (SDR) SDRAM

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=502&partno=2

SDR transfers data only on one clock edge and is slower than DDR (which uses both edges).

Before you perform a timing analysis, make sure to add appropriate pin capacitance to the FPGA I/O pins (the flash and SDR SDRAM data sheets will have their pin capacitance values).

If you've never done this before, look at the example design in this thread (its not for SDR SDRAM, but the concepts are similar);

http://www.alteraforum.com/forum/showthread.php?t=41009

Cheers,

Dave