DE2-115 : position of data pin of FLASH and SDRAM

DQS is a double-data-rate DDR SDRAM signal. The DE2-115 contains single-data-rate (SDR) SDRAM

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=502&partno=2

SDR transfers data only on one clock edge and is slower than DDR (which uses both edges).

Before you perform a timing analysis, make sure to add appropriate pin capacitance to the FPGA I/O pins (the flash and SDR SDRAM data sheets will have their pin capacitance values).

If you've never done this before, look at the example design in this thread (its not for SDR SDRAM, but the concepts are similar);

http://www.alteraforum.com/forum/showthread.php?t=41009

Cheers,

Dave