De10 standard Clock and speed issue

Hi,

I'm a little confused on the clock issues, I'm working on Liunx based system with the debug mode.

I created a flag signal that it will flip in 50us.

I posted the signal from the FPGA to the HPS and send it to the GPIO1. So the signal is a HPS side signal.

Then I exported the same FPGA signal to the other GPIO2. The signal then become a FPGA side signal.

I tested the latency of both signals, the latency is around 1-1.5 us.

I assume the latency is duel to avalon mm bridge reading/writing and CPU latency.

But I don't know which is the main issue.

Also I found some resources on clock system of the SOC boards. And as usual I get more confused.

I have the following questions:

1.The hps default settings show that MPU clock is 950Mhz, debug clock is 12.5Mhz, and FPGA clock is 50Mhz. If I use makefile to generate the userspace program then which clock is used?

2.Do you guys have ways to test how many times one code line use? Or does Cyclone V CPUs have a test code to show a standard tick use for a test code?

3. If using avalon mm bridge latency is the main issue then can that be reduced or is there another way to let the HPS read the FPGA signals?

4.How can I use a faster clock other than the debug clock?

That's all.

Thank you for your help.

reguards.