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CAlex's avatar
CAlex
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2 years ago

De10 standard Clock and speed issue

Hi, I'm a little confused on the clock issues, I'm working on Liunx based system with the debug mode. I created a flag signal that it will flip in 50us. I posted the signal from the FPGA to the...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


From my understanding, the settings are carried over by the handoff folder from Quartus when you build the U-boot, which is why the U-boot need to be regenerated when changing the HPS IP's settings.


Maybe you could use the default image from Terasic and see if using the default differs or seeing the same issue using the default clock settings?


  • CAlex's avatar
    CAlex
    Icon for Contributor rankContributor
    2 years ago

    Good idea, I will have a try.