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CAlex's avatar
CAlex
Icon for Contributor rankContributor
3 years ago

De10 standard Clock and speed issue

Hi, I'm a little confused on the clock issues, I'm working on Liunx based system with the debug mode. I created a flag signal that it will flip in 50us. I posted the signal from the FPGA to the...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


When you mentioned "I created a flag signal that it will flip in 50us", does it only have latency issue with 50us? Did you do any other testing?


  • CAlex's avatar
    CAlex
    Icon for Contributor rankContributor
    3 years ago

    Hi,

    It is done in the FPGA side, and everything in my userspace code is based on that signal.

    So I assume it is the start point flag of my whole userspace system.

    The test was done and the signal was complete and stable when I read the GPIO 2 channel by the oscilloscope.

    reguards.