DE10-Nano Kit vs DE0-Nano-SoC Kit/Atlas-SoC Kit : Which to procure?

Honored Contributor

8 years ago

That's interesting; at this link they say the DE10 part has one hard memory controller in the lower right corner:

Whereas for the DE0 part, it shows two controllers (N suffix does not work):

I could be wrong, but I get the impression that there is always a hard memory controller inside the Cyclone V HPS,

and there are optional hard memory controllers outside of the HPS based on the particular part.

From the Cyclone V device overview:

"Cyclone V devices support up to two hard memory controllers for DDR3, DDR2, and LPDDR2 SDRAM

devices. Each controller supports 8 to 32 bit components of up to 4 gigabits (Gb) in density with two chip

selects and optional ECC. For the Cyclone V SoC devices, an additional hard memory controller in the

HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices."

In Table 10 of the same document, it lists the SE max resource count of the FPGA hard memory controller

from the HPS hard memory controller in separate rows.

If this interpretation is correct, then perhaps the SE device part selector in Cyclone V device overview

manual refers to the number of hard memory controllers outside of the HPS, and the web link above that

I reference describes the total number of hard memory controllers inside the entire part.

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