DE1-SoC: FT UART starts transmitting invalid data after cable is plugged.

One step forward : baudrate must be set up to 115200, and I start getting below data;

now : how to stop it and get the TX for the FPGA ...???

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U-Boot SPL 2013.01.01 (Aug 17 2016 - 15:27:26)

BOARD : Altera SOCFPGA Cyclone V Board

CLOCK: EOSC1 clock 25000 KHz

CLOCK: EOSC2 clock 25000 KHz

CLOCK: F2S_SDR_REF clock 0 KHz

CLOCK: F2S_PER_REF clock 0 KHz

CLOCK: MPU clock 800 MHz

CLOCK: DDR clock 400 MHz

CLOCK: UART clock 100000 KHz

CLOCK: MMC clock 50000 KHz

CLOCK: QSPI clock 400000 KHz

RESET: WARM

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INFO : Watchdog enabled

SDRAM: Initializing MMR registers

SDRAM: Calibrating PHY

SEQ.C: Preparing to start memory calibration

SEQ.C: CALIBRATION PASSED

SDRAM: 1024 MiB

ALTERA DWMMC: 0

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