Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

DE1 SDRAM (again!)

I think this is the right forum for this, because it involves several different components. Basically I am having the same problem many people on this forum seem to have had, but I have had no ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

hi, I've been running through the same problem.

I'm using DE2-115 and tried to use SDRAM in my project (currently just a test project, including only NIOS II Processor, Jtag-UART, and SDRAM Cotroller). I tried to use PLL to manually set the clock signals, instead of using the IP provided by the altera university program as in the tutorial.

I think you should set the clock signal connected to niosII processor to be phase shift (-3.0ns) and connect to undisturbed signal to DRAM_CLK. I got no verification error in this way. (I'm a newbie here, correct me if i"m wrong)

But when try to run some simple C program through NIOS2EDS, no output can be shown.

And also I've problems set the clock signals to a higher frequency, still searching for solutions :(