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Altera_Forum's avatar
Altera_Forum
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15 years ago

DE1 SDRAM (again!)

I think this is the right forum for this, because it involves several different components. Basically I am having the same problem many people on this forum seem to have had, but I have had no ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

This could happen alot of different things. I remember SDRAM phase shift from -2.5 to 4.0 ns in PLL. But the default is -0.75 ns.

1. Pins assigment set incorrect.

2. Reset_n and Clock assignment different pins.

3. Incorrect SDRAM in SOPC builder.

If all of these things are correct. You don't see the failed in NIOS. It's good you post your design Quartus, SOPC Builder configure.

Best regards,

Sean