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Altera_Forum
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13 years ago

DE0 SDRAM Access

Hello :) First time FPGA user here. I'm a University student currently working on a project using a DE0 dev board. I've spent a good hour poking around on these forums trying to find what I'm l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi Jacki2ya:

The Bank/Row/Column addressing scheme of drams/ sdrams is basically a way to reduce the number of pins required when accessing the ram.

Since the ram is a Dynamic Ram based design, there are different rules associated with opening banks, and refreshing the ram that need to be followed. If you truly want to write your own controller, I suggest you download the zentel datasheet for the ram, and start going through the timing diagrams, and understanding the ram chip.

Otherwise, you can you an SOPC/QSYS ram controller from the example system, and just create you own "Avalon" master to control the ram directly, by cutting the appropriate parts out of the system and tying it to your own master.

The Avalon bus system is simpler than SDRAM controller, and closer to what you want in terms of address the ram, but either way you are writing code to talk to a standard interface, that you will have to read the datasheet/specification to understand.

If you want to talk directly to the Zentel ram, go to the Zentel website, and download the spec for the ram device in on the DE0 board.

If you want to try the Avalon approach, search on google for Avalon Bus Specification, and download the spec.

Pete