Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi everyone,
I solved the issue. module test(clock, led); input clock; // wire output led; reg led; reg [31:0] ctr=0; parameter max = 5000; // Execute the assign expressions on every rising edge of the clock always @ (posedge clock) begin ctr <= (ctr == max) ? 0 : ctr + 1; led <= (ctr == max) ? led^1 : led; end endmodule Regards Manos