Forum Discussion
Ganesh_sf
New Contributor
New ContributorDDR4 test failluer with BTS
Hello, The development board I'm using is the Arria 10 SOC (10AS066N3F40E2SG). We attempted to use BTS for DDR4, but we were unable to carry out a flawless test. For further clarification, please re...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Ganesh,
The example design that I have shared is targeting the HILO memory on HPS.
By default, the HILO memory on HPS is 1GB.
I will provide another example design that targeting HILO memory on FPGA (2GB).
Please verify that the development kit is set to default setting.
You may refer to Arria 10 SOC Development Kit User Guide in the link below.
3.2. Default Switch and Jumper Settings (intel.com)
Regards,
Adzim
- AdzimZM_Altera
FPGA HILO memory example design 2GB.
