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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

DDR4 compile conflict with existing constrains

Dear Support/Expert, While I am leaning how to compile a DDR4 with Quartus Pro. I got a message Error(175011): Conflicting region assignments found for DQ_GRP, which is within External Memor...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    Hi David,


    I can see the alert_n pin that you disabled.

    Actually the alert_n pin configuration is in the EMIF IP.

    When you open the EMIF IP in IP Parameter Editor, under the Memory tab, in Topology section, there is a ALERT# pin placement option.

    The EMIF IP will reserve the location that you have set for the alert_n pin.


    In your project, I can see that you set it to I/O Lane with DQS Group 0.

    So the pin location should be in the Bank 2L where there is your DQS Group 0 - 3.

    Because the alert_n pin is not been set by the user, the Quartus will set it for you.

    In this case, I can see that the Quartus has set it to pin C28.

    So now you can change the pin location from E35 to C28 or just let the Quartus set it for you.


    I generate the .tcl file from the Pin Planner in case you want to refer the pin location that have been changed.

    But I also share the .qsf file to ease your work.

    Don't worry on how to use it.

    It's just for reference purpose.

    I'm sorry for confusing you.


    Please let me know if you're still having trouble with it.


    Thanks,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,

I think that the ALERT pin is special pin for the DDR4 interface.

Even if the pin is not assigned by the user, the pin will be assigned by the Quartus as shown in image below.

The Quartus will fit the location for the signal for you.

If you want to use the pin E35, you must change the setting in EMIF IP for ALERT pin location.

As you can in the image below, the setting is set to Address/Command lane 0 with pin no. 8.

This location is also same as pin E35.

But the location is already been used by other signal.

So the ALERT pin location will be determined in this EMIF IP setting and you should aware of where you should assign the pin.

Thanks for posting your question in Intel Community.

Regards,

Adzim

dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago

Hi Adzim,

Now I have another headache. the whole project I am porting to the Intel A10 GX dev board is based on 64 bit DDR4.

if I use the preset DDR4 HiLO 72 bits, then I have to change all the MM bus of the project from 512 to 576( DDR X 8).

if I change preset DDR4 HiLO to 64 bits, then the Alert# won't be able to assign to Pin_E35. I am not that familiar with the DDR4 standard, is this Alert# very critical? can I ignore it when prototype with the Dev Kit, and make the fix in the final production board design?

thank you,

David