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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

DDR4 compile conflict with existing constrains

Dear Support/Expert, While I am leaning how to compile a DDR4 with Quartus Pro. I got a message Error(175011): Conflicting region assignments found for DQ_GRP, which is within External Memor...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    Hi David,


    I can see the alert_n pin that you disabled.

    Actually the alert_n pin configuration is in the EMIF IP.

    When you open the EMIF IP in IP Parameter Editor, under the Memory tab, in Topology section, there is a ALERT# pin placement option.

    The EMIF IP will reserve the location that you have set for the alert_n pin.


    In your project, I can see that you set it to I/O Lane with DQS Group 0.

    So the pin location should be in the Bank 2L where there is your DQS Group 0 - 3.

    Because the alert_n pin is not been set by the user, the Quartus will set it for you.

    In this case, I can see that the Quartus has set it to pin C28.

    So now you can change the pin location from E35 to C28 or just let the Quartus set it for you.


    I generate the .tcl file from the Pin Planner in case you want to refer the pin location that have been changed.

    But I also share the .qsf file to ease your work.

    Don't worry on how to use it.

    It's just for reference purpose.

    I'm sorry for confusing you.


    Please let me know if you're still having trouble with it.


    Thanks,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,


I can see the alert_n pin that you disabled.

Actually the alert_n pin configuration is in the EMIF IP.

When you open the EMIF IP in IP Parameter Editor, under the Memory tab, in Topology section, there is a ALERT# pin placement option.

The EMIF IP will reserve the location that you have set for the alert_n pin.


In your project, I can see that you set it to I/O Lane with DQS Group 0.

So the pin location should be in the Bank 2L where there is your DQS Group 0 - 3.

Because the alert_n pin is not been set by the user, the Quartus will set it for you.

In this case, I can see that the Quartus has set it to pin C28.

So now you can change the pin location from E35 to C28 or just let the Quartus set it for you.


I generate the .tcl file from the Pin Planner in case you want to refer the pin location that have been changed.

But I also share the .qsf file to ease your work.

Don't worry on how to use it.

It's just for reference purpose.

I'm sorry for confusing you.


Please let me know if you're still having trouble with it.


Thanks,

Adzim


dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago

Hi Adzim

Thank you again for the helping. I guess this is not a critical signal, so I can temporary commented it out and going forward. but I did play with the IP for a while, and here is the observation. I created a new example from scratch using 10AX DEv board example. by default the mem_alert_n was assigned to Pin_E35. and the example couldn't compile by default. the error message is very similar to the one that I have. see attached the qar file, and the error message I copied during the compilation. I am new and don't fully understand what does it mean like

Info(175014): Component must be in region from (78, 196) to (78, 207) due to the following assignment(s).

once I comment mem_alert_n at Pin_E35, everything will compile successful.

I guess there may be some tricky stuff not special to my project.

again, I am very grateful to your in-depth help. and in short term I believe I will post a lot question on the forum. hope continuously to get your support.

Best Regards,

David