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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

DDR4 compile conflict with existing constrains

Dear Support/Expert, While I am leaning how to compile a DDR4 with Quartus Pro. I got a message Error(175011): Conflicting region assignments found for DQ_GRP, which is within External Memor...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    Hi David,


    I can see the alert_n pin that you disabled.

    Actually the alert_n pin configuration is in the EMIF IP.

    When you open the EMIF IP in IP Parameter Editor, under the Memory tab, in Topology section, there is a ALERT# pin placement option.

    The EMIF IP will reserve the location that you have set for the alert_n pin.


    In your project, I can see that you set it to I/O Lane with DQS Group 0.

    So the pin location should be in the Bank 2L where there is your DQS Group 0 - 3.

    Because the alert_n pin is not been set by the user, the Quartus will set it for you.

    In this case, I can see that the Quartus has set it to pin C28.

    So now you can change the pin location from E35 to C28 or just let the Quartus set it for you.


    I generate the .tcl file from the Pin Planner in case you want to refer the pin location that have been changed.

    But I also share the .qsf file to ease your work.

    Don't worry on how to use it.

    It's just for reference purpose.

    I'm sorry for confusing you.


    Please let me know if you're still having trouble with it.


    Thanks,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,


Thanks for sharing the qar file and the information regarding to problem.

I need some time to work on this.

I will feedback to you later.


But may I know which Quartus Pro version that you used?


Thanks,

Adzim


  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    4 years ago

    Hi Adzim

    I am using the 21.3.0 Pro. the original design is 64 bits DDR4, but not Hilo formfactor, so besides I did an auto IP upgrade for all IPs, I manually generate the Quartus provided example Hilo IP for Arria 10 GX dev board. and modified it from 72 bits to 64 bits. I am not sure I did it correctly, but it will compile without the pin assignment, once I assign the pin following the Dev board schematic, then the Quartus will report resource conflict. I don't know how to over come the gap between the two EMIF IP.

    Thank you,

    David