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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

DDR4 compile conflict with existing constrains

Dear Support/Expert, While I am leaning how to compile a DDR4 with Quartus Pro. I got a message Error(175011): Conflicting region assignments found for DQ_GRP, which is within External Memor...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    Hi David,


    I can see the alert_n pin that you disabled.

    Actually the alert_n pin configuration is in the EMIF IP.

    When you open the EMIF IP in IP Parameter Editor, under the Memory tab, in Topology section, there is a ALERT# pin placement option.

    The EMIF IP will reserve the location that you have set for the alert_n pin.


    In your project, I can see that you set it to I/O Lane with DQS Group 0.

    So the pin location should be in the Bank 2L where there is your DQS Group 0 - 3.

    Because the alert_n pin is not been set by the user, the Quartus will set it for you.

    In this case, I can see that the Quartus has set it to pin C28.

    So now you can change the pin location from E35 to C28 or just let the Quartus set it for you.


    I generate the .tcl file from the Pin Planner in case you want to refer the pin location that have been changed.

    But I also share the .qsf file to ease your work.

    Don't worry on how to use it.

    It's just for reference purpose.

    I'm sorry for confusing you.


    Please let me know if you're still having trouble with it.


    Thanks,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,


May I have your design for me to replicate the error?


Thanks,

Adzim


  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    4 years ago

    Hi Adzim
    Thank you so much if you can give me some deep help. this is a demo project that shows how to collect data through JESD204B. original project is on 10AX115H2F34E1SG(Standard version 15.1.0). My goal is to port it to Intel GX dev board. 10AX115S2F45I1SG. I have two major tasks, first is the original design was not based on Hilo memory card, so I need mapping the pins from original pin name to Intel Dev board. ( there is a mapping chart in the Intel released schematic, but I am not 100% sure I did it correct, because I don't have a Hilo memory card schematic). Second is the tooling upgrade. I don't really mind it is a standard version or pro, as I got a Pro License with the Dev Kits, so better to use Pro.
    I have been doing the logic/circuit design for a long time, but not very familiar with the Platform Designer and Arria 10 family. I don't have a clear route to trouble shoot this compilation fail problem, I have watched few training video, and browsed some user guide. because of the short time, I haven't figure out a way to do this.
    I attached a .qar file. even I commented out few pin assignment which will fail the fitter, it still failed fitter, the assignments are required by the Hilo DDR4 memory card, so location should not be changed.
    Appreciate your help
    David