DR6
New Contributor
New ContributorDDR3 use from FPGA - DE10-Standard
Hello, I am using the Terasic's DE10-Standard Dev-Board (Cyclone V SX SoC—5CSXFC6D6F31C6N) and I wanted to access the DDR3 SDRAM memory directly from the FPGA (No DMA). But I cannot make it work,...
I'm not sure that you're coding for waitrequest correctly. If waitrequest is high when you issue a read or write command, you have to maintain the control signaling until it goes low. You don't have any code for this situation. It looks like you're bouncing between the IDLE and READ and WRITE states with the control signals going back and forth between high and low. You should stay in the IDLE state until waitrequest goes low.
