Forum Discussion

DR6's avatar
DR6
Icon for New Contributor rankNew Contributor
1 year ago
Solved

DDR3 use from FPGA - DE10-Standard

Hello, I am using the Terasic's DE10-Standard Dev-Board (Cyclone V SX SoC—5CSXFC6D6F31C6N) and I wanted to access the DDR3 SDRAM memory directly from the FPGA (No DMA). But I cannot make it work,...
Fpga Devkit
  • sstrell's avatar
    sstrell
    1 year ago

    I'm not sure that you're coding for waitrequest correctly. If waitrequest is high when you issue a read or write command, you have to maintain the control signaling until it goes low. You don't have any code for this situation. It looks like you're bouncing between the IDLE and READ and WRITE states with the control signals going back and forth between high and low. You should stay in the IDLE state until waitrequest goes low.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

I'm not sure that you're coding for waitrequest correctly. If waitrequest is high when you issue a read or write command, you have to maintain the control signaling until it goes low. You don't have any code for this situation. It looks like you're bouncing between the IDLE and READ and WRITE states with the control signals going back and forth between high and low. You should stay in the IDLE state until waitrequest goes low.

  • DR6's avatar
    DR6
    Icon for New Contributor rankNew Contributor
    1 year ago

    Thanks for the reply. I was reviewing the code after your reply, and with some time perspective (I wrote it some days ago), I also think it is not properly coded. I will definitely take a look at that.