library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mem_controller is
    port(
        -- Señales de la interfaz Avalon-MM
        clk                      : in  std_logic;
        rst_n                    : in  std_logic;
        sdram_data_addr          : out std_logic_vector(28 downto 0);
        sdram_data_burstcount    : out std_logic_vector(7 downto 0);
        sdram_data_waitrequest   : in  std_logic;
        sdram_data_readdata      : in  std_logic_vector(63 downto 0);
        sdram_data_readdatavalid : in  std_logic;
        sdram_data_read          : out std_logic;
        sdram_data_writedata     : out std_logic_vector(63 downto 0);
        sdram_data_byteenable    : out std_logic_vector(7 downto 0);
        sdram_data_write         : out std_logic;
        -- Señales de control
        do_read                  : in  std_logic;
        do_write                 : in  std_logic;
        write_data               : in  std_logic_vector(63 downto 0);
        read_data                : out std_logic_vector(63 downto 0);
        read_data_valid          : out std_logic;

        state_out                : out std_logic_vector(1 downto 0)
    );
end entity;

architecture rtl of mem_controller is
    -- Definición de estados para la máquina de estados
    type state_type is (IDLE, WRITE, READ, WAIT_FOR_READ);
    signal state : state_type;

    -- Señales internas
    signal address_counter : std_logic_vector(28 downto 0) := "00100000000000000000000000000";
begin
    -- Proceso síncrono para la máquina de estados
    process(clk, rst_n)
    begin
        if rst_n = '0' then
            -- Inicialización de señales en caso de reset
            state <= IDLE;
            sdram_data_addr <= (others => '0');
            sdram_data_burstcount <= (others => '0');
            sdram_data_read <= '0';
            sdram_data_write <= '0';
            sdram_data_byteenable <= (others => '0');
            read_data <= (others => '0');
            read_data_valid <= '0';
            address_counter <= "00100000000000000000000000000";
        elsif rising_edge(clk) then
            case state is
                when IDLE =>
                    -- Estado de espera para operaciones de lectura o escritura
                    if do_write = '1' then
                        sdram_data_addr <= address_counter;
                        sdram_data_writedata <= write_data;
                        sdram_data_byteenable <= (others => '1'); -- Habilitar todos los bytes
                        sdram_data_burstcount <= "00000001"; -- Burst de 1
                        sdram_data_write <= '1';
                        state <= WRITE;
                    elsif do_read = '1' then
                        sdram_data_addr <= address_counter;
                        sdram_data_byteenable <= (others => '1'); -- Habilitar todos los bytes
                        sdram_data_burstcount <= "00000001"; -- Burst de 1
                        sdram_data_read <= '1';
                        state <= READ;
                    end if;

                    state_out <= "11";

                when WRITE =>
                    -- Manejo de la operación de escritura
                    if sdram_data_waitrequest = '0' then
                        sdram_data_write <= '0';
                        --address_counter <= std_logic_vector(unsigned(address_counter) + 1);
                        state <= IDLE;
                    end if;

                    state_out <= "01";

                when READ =>
                    -- Manejo de la operación de lectura
                    if sdram_data_waitrequest = '0' then
                        sdram_data_read <= '0';
                        state <= WAIT_FOR_READ;
                    end if;

                    state_out <= "10";

                when WAIT_FOR_READ =>
                    -- Espera de datos válidos después de una lectura
                    if sdram_data_readdatavalid = '1' then
                        read_data <= sdram_data_readdata;
                        read_data_valid <= '1';
                        --address_counter <= std_logic_vector(unsigned(address_counter) + 1);
                        state <= IDLE;
                    end if;

                    state_out <= "00";

                when others =>
                    state <= IDLE;

                    state_out <= "11";
            end case;
        end if;
    end process;
end architecture;