Altera_ForumHonored Contributor14 years agoDDR3 Timimg requirementsHi, What changes should be done to meet DDR3 Timing requirements if I am migrating my project from use of EP2AGX125EF35c4 as FPGA to EP2AGX125EF35i5 as FPGA ?
Recent DiscussionsRegarding data for the Altera Arria V GX FPGA development kitAXC3000 Agilex 3 boardAccess to System MAX design for Agilex 5 kitSolvedAgilex 5 reconfigurable PLL - emifAgilex7 m-series for llama