DDR3 fitter 失败

Hi,

I compiled your design and reproduce the error seen. The error is due to a known issue of a fitter bug associated with HPS EMIF pinouts. I have added an INI variable to a quartus.ini file in your project to bypass this fitter check and it now compiles successfully. Attached is the .qar project with INI.

In summary, below is my checking results:

1) To enable your project to fit, add a quartus.ini file to your top level project directory with this INI variable: emif_restrict_hps_refclk_to_ac_tile=off

2) I looked over the pinouts of and the following comments:

ddr3 : pinout all OK

2A : DQS groups 1,2,3

2B : DQS groups 0, address/command, pll ref clock, RZQ

emif_hps : pinout all OK. More extra info regarding hps alert pin in below comment.

2L : DQS groups 4,5,6,7 - OK

2M : address/command, pll ref clock, RZQ - OK

2N : DQS groups 0,1,2,3 - OK ; alert pin on location LVDS2N_24p with DQS group 0 – followed as what mentioned in UG which is correct .

HPS alert pin comments:

Refer to the Stratix 10 EMIF IP UG Figure 17 on page 41.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-emi.pdf

See the light grey colour shading with recommended locations for ALERT_N (LVDS2N_24p or 18p)

The main reason for recommending alert to be in the two specified locations(24p and 18p) is to allow flexibility to vary the width of the HPS DDR4 interface.

For your fitter bug, I would expect this to compile successfully in a future Quartus release when this bug is fixed (anticipated 20.1) without needing the INI variable.

Hope this explanation makes sense but let me know if you have any questions.

Thanks

Regards,

Aida