DDR phase offset Cyclone III Dev Kit

I'm following the tutorial "Using DDR and DDR2 SRAM Devices in Cyclone III devices" from the External Memory Interfaces guide.

On page 3-18 it says "Modify the clk2 phase setting to -55 degrees, and recompile the design".

If I do that, I get a timing error, saying that the phase difference between clock1 and clock2 must between 72 and 108 degrees.

Is that due to a change in the DDR2 Ram timing analysis code since the tutorial was written, or am I doing something wrong?

regards

Alan