DCFIFO and AD9433 problem

Unfortunately, i don't understand what you are exactly doing. Can you please tell about the involved ADC and DAC sampling rates and how the FIFO source and sink handshake signals (wrreq, rdreq, full, empty) are connected?

By the way, it's impossible to replay the ADC signal at a different rate continously. If you see a higher DAC output frequency (I assume you actually measure the output signal) than the ADC input signal has, it means that a block of data is repeated multiple times. You should be aware of, if you look sharp on it.