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Altera_Forum
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11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Now I still have problems configuring SignalTap II:

as stated in posts# 54 to# 57 I can't see the "first" edge of the trigger, even when waiting for a long time after starting the acquisition and before starting the process. Surely my configuration is bad but I can't find the problem.

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Try a different solution then.

For example. Rather than trigger off your asynchronous signal, trigger off a counter inside the FPGA. Have that counter enabled by your external signal, but first make sure that external signal is synchronized to the clock used by SignalTap II and the counter. Then trigger off the counter, eg., a count of 1.

Doing this may make you realize what you were doing wrong earlier.

Cheers,

Dave