Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Now I still have problems configuring SignalTap II:

as stated in posts# 54 to# 57 I can't see the "first" edge of the trigger, even when waiting for a long time after starting the acquisition and before starting the process. Surely my configuration is bad but I can't find the problem.