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Altera_Forum
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11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Sorry I was away for the work.

Now I'm back on this project. I instantiated a fifo, I've got a qsys system with a Nios II cpu. This system has access to the fifo but I'm lost: has the JTAG to Avalon master bridge you use to be implemented? The signals from the fifo have to go to the sdram controller or to the cpu? The commands you use (as jtag_read or jtag_write) can be used by the cpu or only in the console?