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The CycloneIII starter board has the MSEL0-3 bits tied to ground
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Are you using a different board than DK-START-3C25N? It has MSEL wired permanently for AP 2.5V configuration according to the circuit diagram, as necessary for the flash device assembled to the board. JTAG configuration is always possible in addition.
Regarding the buffers connected to overcome the strange open drain issue, I attached the modified project with my previous post, you can check yourself. I think the point is, that something has to be connected to the pin at all.
The pin options for a DDR memory controller are normally set by a script file, it would be sufficient to import it to the design. But it can happen, that you miss this step and then several placement rules in effect with SSTL may be violated. The rule are documented in Cyclone III handbook and also in application notes. If you e.g. would set all DDR pins in the design to the required SSTL-2 standard without some additional definitions, you get a lot of errors. Reviewing the DDR pin assignments in Altera provided example designs, e. g. cycloneIII_3c25_start_niosII_standard can help to understand the requirements.
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