CycloneIII Starter Board

Hallo Brian,

I tried to compile your design and found some assignment errors. You assigned incompatible IO standards to some pins,the board is using VCCIO of 2.5V at all banks. Also some dual-purpose pins haven't been set to regular I/O, which is necessary, als already discussed.

After these changes, I get still the reported errors for two pins:

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Error: Following feature(s) of I/O pin FLASH_SRAM_DQ0 has invalid setting(s) in configuration scheme ACTIVE_SERIAL when the pin is placed at pin location H3

Info: The IO feature 'Open Drain' has invalid setting, it should set to OFF

Error: Following feature(s) of I/O pin FLASH_SRAM_DQ1 has invalid setting(s) in configuration scheme ACTIVE_SERIAL when the pin is placed at pin location D1

Info: The IO feature 'Open Drain' has invalid setting, it should set to OFF

--- Quote End ---

The fact, that no Open Drain option is actually set indicates, that we are experiencing a Quartus bug in this case, to my opinion. Also, a basic oddity is this: Although the Starter Board is using AP configuration, you can't set AP configuration in Device Options without generating a shower of errors. The example designs shipped with the Starter Board have their configuration set arbitrarily to AS, seems to be some kind of bug work-around.

Apparently another secret option allows the example design to use the same pins as your design without generating the reported silly open drain error. Perhaps another user knows about, otherwise Altera support must fix the problem.

Regards,

Frank

P.S.: I found a solution. connecting a bidirectional buffer to the affected pins allowed the design to compile.

By the way, you can expect further exciting experiences when connecting the DDR II pins. I suggest to read thorougly what's been said regarding placement rules and the neccesity to define output enable groups with bidirectional SSTL IO pins.