Forum Discussion
Jodok
New Contributor
New ContributorCyclone V TSE MAC timing closure
I try to synthesize a tripple speed ethernet (TSE) MAC with rgmii on 5CGTFD9E5F31l7 and encounter timing missmatches. The PHY is a DP83867IR and a TXV0106 level-shifter (+/- 0.3ns skew) is inbetween...
RichardT_altera
Super Contributor
Super ContributorHi,
It's been a while since your last reply.
May I know if the issue has been resolved, or if you still need assistance with this case?
If so, could you kindly share your design by archiving the project (Project > Archive Project) so that I can investigate it further.
Regards,
Richard Tan
