Forum Discussion

MKlee2's avatar
MKlee2
Icon for New Contributor rankNew Contributor
5 years ago

Cyclone V SoC - Recommend way to access HPS-SD-Ram

Kind of a beginner question, I want to write to my HPS memory from the fpga side. (I already reserved 512MB)

Up till now I used the FPGA-to-HPS SDRAM bridge an wrote data direktly to the Avalon-MM interface. But whenever I read references I see people recommend using a mSGDMA, so whats the benifit of using a DMA here?

Is it faster, uses it less resources or anything?

Cause I'm kind of new to this topic I would also be happy if you cpuld link me some base material to it.

Unrelated to the Cyclone V, but latly I started to work with an Stratix10 PCI-E expansion card and read that using a DMA here is necessary to reduce CPU overhead when accessing memory, does this also apply to the Cyc V?

As I said I'm pretty new to this topic so if you have any interesting material I can read up about all this it would be nice to share it with me.

1 Reply

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hello,

    Data transfer between FPGA and HPS is critical and this is one of the benefits of having FPGA SoC devices. the transfer speed might vary based on your design requirements. the efficient way of transferring data from source to destination without loading the processor/controller/state-machine is the DMA. So with DMA, you can set the source address, destination address, and the amount of data, and thats it. DMA will do the magic for you.

    mSGDMA is the advanced version of DMA. with mSGDMA, you can set multiple sources and multiple destinations with various sizes of data. You can refer to this video to show you the basic concepts of initializing this IP:

    https://www.youtube.com/watch?v=iaRkjkpMBH8

    This video is just a demo case, it used Nios II to control the mSGDMA and transfer the data from memory to memory inside the FPGA. In your case, everything should be the same, except the controller might be the HPS, and the destination might be the SDRAM bridge.

    Thank you