Forum Discussion
Jodok
New Contributor
New ContributorCyclone V: reaching RGMII Data to Clock output skew of +/- 500ps
What is best practice to reach the 500ps Data to Clock output Skew of RGMII specification v2.0 on a Cyclone V? Trying synthesizing a TSE MAC with RX-Clock to TX-Clock loopback fails because of timin...
ShengN_altera
Super Contributor
Super ContributorHi,
Seems like there's no problem with the timing equation. Most probably the problem due to some parameter is wrong or missing. I think you may need to open an IPS thread https://www.intel.com/content/www/us/en/support/articles/000057045/ethernet-products.html to get some insights from RGMII expert.
