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Jodok's avatar
Jodok
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

What is best practice to reach the 500ps Data to Clock output Skew of RGMII specification v2.0 on a Cyclone V? Trying synthesizing a TSE MAC with RX-Clock to TX-Clock loopback fails because of timin...
Fpga Devkit
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Even without the tracedelay, the setup still fail. Could you try with PHY with delay option disabled, does the timing pass?


Seems like there's something wrong with the parameter used.