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Jodok
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2 years ago

Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

What is best practice to reach the 500ps Data to Clock output Skew of RGMII specification v2.0 on a Cyclone V? Trying synthesizing a TSE MAC with RX-Clock to TX-Clock loopback fails because of timin...
Fpga Devkit
Jodok's avatar
Jodok
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2 years ago

Hi Sheng

Yes, I still use a PHY with delay option of 2ns enabled.

Combination 1 seems the correct one to me. This is what I was doing originally.

But still, with exact this combination TA fails with -0.065ns max slack -40°..+100°C both, fast and slow model analyzed.

Combination 2 seems to be ilegitime, since tx_min_delay has to be smaller than tx_max_delay.

Combination 3 would theoretically be legal since tx_min_delay is smaller than tx_max_delay, but since the formula is the same as for Combination 2, it is false as well.

I will try to find other resources to get on.

Thank you Sheng.