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Jodok
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1 year ago

Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

What is best practice to reach the 500ps Data to Clock output Skew of RGMII specification v2.0 on a Cyclone V? Trying synthesizing a TSE MAC with RX-Clock to TX-Clock loopback fails because of timin...
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Jodok
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1 year ago

Hi Sheng,

thank you for your response!

How does one then respect the "asymmetrical" characteristic of the Delay introduced by the PHY?

Could you please review the following constraints for a ddr transmission.

max_delay = tData(max) + tSU - (tPeriod/2 - tPHYDELAY)

min_delay = tData(min) - tH - (tPeriod/2 - tPHYDELAY)

Thank you very mouch.