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AShiv's avatar
AShiv
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7 years ago

Cyclone V Nios/FPGA Configuration

Hi everyone,

I have a Cyclone V E Development board, and I am trying to figure out how to set up the system I'm trying to build. Or if its even possible. So what I want to do is have the Nios II run off the DDR3 external memory, but also have the FPGA be able to write to said DDR3, and have the TSE have access to said DDR3. However, only one would be writing to said part of the DDR3 at a time. So, the Nios would have its app code copied from the Flash to the DDR3 and run off of it. The FPGA will write some data to the DDR3, signal Nios that its ready. Nios will then point the TSE core to the data and the TSE will send it out. So only one master will access the DDR3 data buffer at a time. I was wondering if anyone has an example of doing multiple masters with the DDR3? Also, For the flash boot section, I know its possible, but I cant seem to figure out how to configure the flash serial controller since I don't know what the type is in Qsys. If anyone can point me in the right direction on any of that id appreciate it, Thanks!

2 Replies

  • Abe's avatar
    Abe
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Which kit are you using?

    Does the FPGA kit have the ARM core HPS in it and is the DDR3 connected to HPS side or to the FPGA side .

    Is the TSE also connected to HPS or FPGA fabris?

    You will need to find answers for this to start your design, as the Cyclone V has two variants, the FPGA alone variant as well as the ARM SoC variant.

  • AShiv's avatar
    AShiv
    Icon for New Contributor rankNew Contributor
    7 years ago

    Oh I'm sorry I thought I put the kit on there, its the Cyclone V E Development Kit: DK-DEV-5CEA7N. There is no ARM processor, its a pure FPGA board, so the TSE is connected to the FPGA fabric. Really my question is how to go about setting up the NIOS to run off the DDR3, as well as having the FPGA be able to have addressable access, and having the TSE have access as well. I was thinking about setting up the DDR3 into three separate sections, two data buffers that could be accessed by the FPGA, NIOS, or TSE. And the last section being the area for the NIOS itself. But I have no idea how to do it.